In a typical integrated circuit formation process, semiconductor wafers, each including a plurality of identical semiconductor chips (also referred to as dies), are manufactured first. After manufacturing, the semiconductor wafers are sawed to separate the semiconductor chips, so that each of the semiconductor chips may be packaged individually.
However, the conventional wafer dicing processes have a number of shortcomings. For example, the upper metal layers on the semiconductor substrate may crack during the process enabling contaminants or moisture to penetrate through the die. Therefore, the failure rate of the overall assembly could increase.
Accordingly, there is a need for an improved method to saw the semiconductor wafer into individual dies with robust electrical performance.